As demand increases for higher density and speed in dynamic random access memories, various approaches have been used to increase the speed of data access. Conventional DRAMs are currently operating in extended data output mode (EDO) in which data lines are not tri-stated between read cycles. Instead, data is held valid after /CAS, or until /RAS is brought high. Complex timing is required to properly time the arrival of valid data at output pins from the input of column addresses.
In synchronous DRAMs (SDRAMs), a system clock is used to synchronize a burst mode operation which essentially consists of inputting an initial start address and then incrementing the subsequent column addresses internally, in response to the system clock cycles. SDRAMs however, require several additional pins compared to conventional DRAMs and as such, are more difficult to fit in within standard memory modules SIMMs. Furthermore, the synchronization of all signals with the system clock requires an additional level of design complexity not required in conventional DRAMs.
U.S. Pat. No. 5,675,549 issued to Ong et al on Oct. 7, 1997 describes a burst EDO memory address counter which consists of two flip/flops and a multiplexer and which can be implemented in EDO DRAM having a standard pin-out compatible with SIMM memory modules. The counter structure provides for linear or interleaved addressing sequences. The counter cell implementation is in fact a 2 bit burst address counter which simply counts the number of addresses required in the burst operation. The multiplexer is used to provide the toggle condition for the next counter bit.
In SRAMs employing burst mode operation, the internal counter used to generate column addresses must be loadable with both external and internal addresses. Typical implementations receiving internal and external address select input signals suffer from a high setup time requirement between these address select signals and the system clock. As a result, the system clock must be delayed significantly to meet the set up time requirements. To reduce this setup time, gated clocks may be employed which reduce the setup time, but carry inherent dangers of flitches which can result by latching spurious column addresses.
A need therefore arises for a counter cell which has minimal setup time, fast propagation delay and ensures robustness of the latched column address.